Computer Architecture and
Power Aware Systems Research Group



May 2007:

  • Two papers from our research group were accepted to the International Conference on Supercompuing (ICS). Check publications page for details.

January 2007:

  • Kanad Ghose and Dmitry Ponomarev received a research grant from Intel to study performance and energy trade-offs in multicore and multithreaded architecures.
  • Paper by Matt Yourst on the design of PTLsim was accepted to ISPASS.
  • Joe Sharkey defended PhD dissertation in December 2006. He joined AIS, Inc. in Rome, NY.

May 2006:

  • Several papers co-authored by the members of our group have been recently accepted to ISLPED, PACT and ICPP conferences. Please check the publications page for details!
  • Shadi Khasawneh defended his MS Thesis and joined Intel Austin Labs

March 2006:

  • Joseph Sharkey, a PhD student in the CS Department and a member of CAPS research group received Graduate School Award for Excellence in Research. Congratulations, Joe!
  • Several students in our group have recently obtained industrial internship positions:
  • Joseph Sharkey will join the Reliability and Power-Aware Microarchitectures group at the IBM Watson Research Center in Yorktown Heights, NY in May 2006 for a summer internship.

    Sumeet Kumar joined Intel Labs for an internship starting in January 2006.

    Deniz Balkan joined Intel Folsom Labs, California in January 2006 for a 9-month co-op position.

    Shadi Khasawneh joined Intel Austin Labs in January 2006 for an internship position.

January 2006:

  • Several papers co-authored by the members of our group have been recently accepted to major conferences. One paper appeared in MICRO 2005 and three more in HPCA 2006. These papers span a wide range of topics, including binary translation, multithreading, reliability-aware microarchitectures and efficient cache designs. Please check the publications page for details!
  • Two new tools designed by our PhD students have been publicly released.

    PTLsim (developed by Matt Yourst) is a cycle accurate microprocessor simulator and virtual machine for the x86 and x86-64 instruction sets. PTLsim models a modern speculative out of order x86-64 compatible processor core, cache hierarchy and supporting hardware. It runs unmodified 32-bit x86 and 64-bit x86-64 applications without special compilers or toolchains.

    M-Sim (developed by Joseph Sharkey) is a multithreaded extension of Simplescalar, which models all key datapath components as separate entities (as opposed to the RUU-based model of Simplescalar), explicitly implements register renaming, supports speculative scheduling and the squash recovery model, and has several other useful features.

    Please check the tools page for details!



Copyright © 2005 CAPS, Designed by: Deniz Balkan & Joe Sharkey