Computer Architecture and
Power Aware Systems Research Group


 

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2009


  • "MPTLsim: A Simulator for x86 Multicore Processors"
    Hui Zeng, Matt Yourst, Kanad Ghose and Dmitry Ponomarev
    46th Design Automation Conference (DAC-2009), San Fransisco, July 2009.
  • "Energy Efficient Renaming with Register Versioning"
    Hui Zeng, Ju-Young Jung, Kanad Ghose and Dmitry Ponomarev
    International Symposium on Low Power Electronics and Design (ISLPED-2009), San Fransisco, August 2009.
  • "An Energy-Efficient Checkpointing Mechanism for Out-of-Order Commit Processors"
    Hui Zeng, Matt Yourst, Kanad Ghose
    International Symposium on Low Power Electronics and Design (ISLPED-2009), San Fransisco, August 2009.
  • "Register Versioning: A Low-Complexity Implementation of Register Renaming in Out-of-Order Microarchitectures"
    Hui Zeng, Kanad Ghose and Dmitry Ponomarev
    38th International Conference on Parallel Processing (ICPP-2009), Vienna, September 2009.
  • "Improving Performance of Simple Cores by Exploiting Loop-Level Parallelism through Value Prediction and Reconfiguration"
    Tameesh Suri, Aneesh Aggarwal
    6th Annual ACM International Conference on Computer Frontiers, May 2009.
  • "Improving Scalability and Per-core Performance in Multi-cores through Resource Sharing and Reconfiguration"
    Tameesh Suri, Aneesh Aggarwal
    22nd IEEE Conference on VLSI Design, January 2009. Best Student Paper Award.

2008


  • "Energy-Efficient MESI Cache Coherence with Pro-Active Snoop Filtering on Multicore Microprocessors"
    Avadh Patel and Kanad Ghose
    International Symposium on Low Power Electronics and Design (ISLPED), August 2008.
  • "Scalable Multi-cores with Improved Per-core Performance using Off-the-critical Path Reconfigurable Hardware"
    Tameesh Suri, Aneesh Aggarwal
    15th IEEE International Conference on High Performance Computing (HiPC), December 2008. Best Paper Award.
  • "Hiding Communication Delays in Clustered Microarchitectures"
    Robert LaDuca, Joseph Sharkey and Dmitry Ponomarev
    20th IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Campo Grande, Brasil, October 2008.
  • "Accurate and Low-Overhead Dynamic Detection and Prediction of Program Phases Using Branch Signatures"
    Balaji Vijayan and Dmitry Ponomarev
    20th IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Campo Grande, Brasil, October 2008.
  • "Aggressive Scheduling and Speculation in Multithreaded Architectures: Is It Worth Its Salt?"
    Jason Loew and Dmitry Ponomarev
    20th IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Campo Grande, Brasil, October 2008.
  • "Two-Level Reorder Buffers: Accelerating Memory-bound Applications on SMT Architectures"
    Jason Loew and Dmitry Ponomarev
    37th International Conference on Parallel Processing (ICPP), September 2008.
  • "Optimizing XML Processing for Grid Applications Using an Emulation Framework"
    Rajdeep Bhowmik, Chaitali Gupta, Mdhusudhan Govindaraju, Aneesh Aggarwal
    International Parallel and Distributed Processing Symposium (IPDPS), April 2008.
  • "Speculative Instruction Validation for Performance-Reliability Trade-offs"
    Sumeet Kumar and Aneesh Aggarwal
    International Symposium on High Performance Computer Architecture (HPCA), February 2008.
  • "Complexity-Effective Bypass Networks"
    Aneesh Aggarwal
    Transactions on High Performance Embedded Architecture and Compilation, August 2008.
  • "Reducing Register Pressure in SMT Processors through L2-Miss-Driven Early Register Release"
    Joseph Sharkey, Jason Loew, Dmitry Ponomarev
    To appear in the ACM Transactions on Architecture and Code Optimization (ACM TACO), 2008 .
  • "Predicting and Exploiting Transient Values for Reduced Register File Pressure and Energy Consumption"
    Deniz Balkan, Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose
    IEEE Transactions on Computers, Vol.57, No 1, January 2008, pp.82-95.
  • "Selective Writeback: Reducing Register File Pressure and Energy Consumption"
    Deniz Balkan, Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, No 6, June 2008, pp.650-661.

2007



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1997



Copyright © 2005 CAPS, Designed by: Deniz Balkan & Joe Sharkey