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2009
-
"MPTLsim: A Simulator for x86 Multicore Processors"
Hui Zeng, Matt Yourst, Kanad Ghose and Dmitry Ponomarev
46th Design Automation Conference (DAC-2009), San Fransisco, July 2009.
-
"Energy Efficient Renaming with Register Versioning"
Hui Zeng, Ju-Young Jung, Kanad Ghose and Dmitry Ponomarev
International Symposium on Low Power Electronics and Design (ISLPED-2009), San Fransisco, August 2009.
-
"An Energy-Efficient Checkpointing Mechanism for Out-of-Order Commit Processors"
Hui Zeng, Matt Yourst, Kanad Ghose
International Symposium on Low Power Electronics and Design (ISLPED-2009), San Fransisco, August 2009.
-
"Register Versioning: A Low-Complexity Implementation of Register Renaming in Out-of-Order Microarchitectures"
Hui Zeng, Kanad Ghose and Dmitry Ponomarev
38th International Conference on Parallel Processing (ICPP-2009), Vienna, September 2009.
-
"Improving Performance of Simple Cores by Exploiting Loop-Level Parallelism through Value Prediction and Reconfiguration"
Tameesh Suri, Aneesh Aggarwal
6th Annual ACM International Conference on Computer Frontiers, May 2009.
-
"Improving Scalability and Per-core Performance in Multi-cores through Resource Sharing and Reconfiguration"
Tameesh Suri, Aneesh Aggarwal
22nd IEEE Conference on VLSI Design, January 2009. Best Student Paper Award.
2008
-
"Energy-Efficient MESI Cache Coherence with Pro-Active Snoop Filtering on Multicore Microprocessors"
Avadh Patel and Kanad Ghose
International Symposium on Low Power Electronics and Design (ISLPED),
August 2008.
-
"Scalable Multi-cores with Improved Per-core Performance using Off-the-critical Path Reconfigurable Hardware"
Tameesh Suri, Aneesh Aggarwal
15th IEEE International Conference on High Performance Computing (HiPC), December 2008. Best Paper Award.
- "Hiding Communication Delays in Clustered Microarchitectures"
Robert LaDuca, Joseph Sharkey and Dmitry Ponomarev
20th IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Campo
Grande, Brasil, October 2008.
-
"Accurate and
Low-Overhead Dynamic Detection and Prediction of Program Phases Using
Branch Signatures"
Balaji Vijayan and Dmitry Ponomarev
20th IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Campo
Grande, Brasil, October 2008.
-
"Aggressive Scheduling and Speculation in Multithreaded Architectures: Is It Worth Its Salt?"
Jason Loew and Dmitry Ponomarev
20th IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Campo
Grande, Brasil, October 2008.
-
"Two-Level Reorder Buffers: Accelerating Memory-bound Applications on SMT Architectures"
Jason Loew and Dmitry Ponomarev
37th International Conference on Parallel Processing (ICPP),
September 2008.
-
"Optimizing XML Processing for Grid Applications Using an Emulation Framework"
Rajdeep Bhowmik, Chaitali Gupta, Mdhusudhan Govindaraju, Aneesh Aggarwal
International Parallel and Distributed Processing Symposium (IPDPS),
April 2008.
-
"Speculative Instruction Validation for Performance-Reliability Trade-offs"
Sumeet Kumar and Aneesh Aggarwal
International Symposium on High Performance Computer Architecture (HPCA),
February 2008.
-
"Complexity-Effective Bypass Networks"
Aneesh Aggarwal
Transactions on High Performance Embedded Architecture and Compilation,
August 2008.
-
"Reducing Register Pressure in
SMT Processors through L2-Miss-Driven Early Register Release"
Joseph Sharkey, Jason Loew, Dmitry Ponomarev
To appear in the ACM Transactions on Architecture and Code Optimization (ACM TACO), 2008 .
-
"Predicting and Exploiting Transient Values for Reduced Register File Pressure and Energy Consumption"
Deniz Balkan, Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose
IEEE Transactions on Computers, Vol.57, No 1, January 2008, pp.82-95.
-
"Selective Writeback: Reducing Register File Pressure and Energy Consumption"
Deniz Balkan, Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose
IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, Vol. 16, No 6, June 2008, pp.650-661.
2007
- "An L2-Miss-Driven Early Register Deallocation for SMT
Processors"
Joseph Sharkey, Dmitry Ponomarev
21st ACM International Conference on Supercomputing (ICS'07),
Seattle, WA, June 2007.
- "Increasing Cache Capacity through Word Filtering"
Prateek Pujara, Aneesh Aggarwal
21st ACM International Conference on Supercomputing (ICS'07),
Seattle, WA, June 2007.
- "PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator"
Matt T. Yourst
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS'07),
San Jose, California, April 2007.
- "Exploiting Operand Availability for Efficient Simultaneous
Multithreading"
Joseph Sharkey, Dmitry Ponomarev
IEEE Transactions on Computers, Vol. 55, No 2, February 2007, pp.208-223.
2006
- "Trade-offs in
Transient Fault Recovery Schemes for Redundant
Multithreaded Processors"
Joseph Sharkey, Nayef Abu-Ghazaleh, Dmitry Ponomarev, Kanad Ghose, Aneesh Aggarwal
To appear in 13th IEEE International Conference on High Performance Computing (HiPC'06),
Bangalore, India, December 2006.
- "Adaptive Reorder Buffers
for SMT Processors"
Joseph Sharkey, Deniz Balkan, Dmitry Ponomarev
To appear in the 15th IEEE/ACM International
Conference on Parallel Architectures and Compilation
Techniques (PACT'06),
Seattle, WA, September 2006.
- "SPARTAN:
Speculative Avoidance of Register Allocations to Transient Values for
Performance and Energy-Efficiency"
Deniz Balkan, Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose
To appear in the 15th IEEE/ACM International
Conference on Parallel Architectures and Compilation
Techniques (PACT'06),
Seattle, WA, September 2006.
- "Self-Checking Instructions:
Reducing Resource Redundancy for Concurrent Error Detection"
Sumeet Kumar, Aneesh Aggarwal
To appear in the 15th IEEE/ACM International
Conference on Parallel Architectures and Compilation
Techniques (PACT'06),
Seattle, WA, September 2006.
- "Selective
Writeback:
Exploiting Transient Values for Energy-Efficiency and Performance"
Deniz Balkan, Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose
To appear in the IEEE/ACM International
Symposium on Low Power Electronics and Design (ISLPED'06),
Tegernsee, Germany, October 2006.
- "Register
File Caching for Energy Efficiency"
Hui Zeng, Kanad Ghose
To appear in the IEEE/ACM International
Symposium on Low Power Electronics and Design (ISLPED'06),
Tegernsee, Germany, October 2006.
- "Balancing ILP
and TLP in SMT Architectures through Out-of-Order Instruction Dispatch
"
Joseph Sharkey, Dmitry Ponomarev
To appear in the 35th International Conference on
Parallel Processing (ICPP), Columbus, OH, August 2006.
- "Address-Value
Decoupling for Early Register Deallocation
"
Deniz Balkan, Joseph Sharkey, Dmitry Ponomarev and Aneesh Aggarwal
To appear in the 35th International Conference on
Parallel Processing (ICPP), Columbus, OH, August 2006.
- "Exploiting
Short-Lived Values for Low-Overhead Transient Fault Recovery
"
Nayef Abu-Ghazaleh, Joseph Sharkey, Dmitry Ponomarev and Kanad Ghose
To appear in Workshop on Architectural Support for
Gigascale Integration, in conjunction with ISCA-33, Boston, MA,
June 2006
- "Efficient
Instruction Schedulers for SMT Processors"
Joseph Sharkey, Dmitry Ponomarev
In the 12th International Symposium on High Performance
Computer Architecture (HPCA-12), Austin, TX, February 2006.
- "Reducing
Resource Redundancy for Concurrent Error Detection Techniques in High
Performance Microprocessors"
Sumeet Kumar, Aneesh Aggarwal
In the 12th International Symposium on High Performance
Computer Architecture (HPCA-12), Austin, TX, February 2006.
- "Increasing the
Cache Efficiency by Eliminating Noise"
Prateek Pujara, Aneesh Aggarwal
In the 12th International Symposium on High Performance
Computer Architecture (HPCA-12), Austin, TX, February 2006.
- "
Dynamic Resizing of Superscalar Datapath Components for
Energy-Efficiency"
Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose
IEEE Transactions on Computers, Volume 55, No 2, February
2006, pp.199-213.
- "
Early Register Deallocation Mechanisms Using Checkpointed Register
Files"
Oguz Ergin, Deniz Balkan, Dmitry Ponomarev, Kanad Ghose
IEEE Transactions on Computers, vol.55, No 9, pp.1153-1166, September 2006.
- "Instruction
Packing: Toward Fast and Energy-Efficient Instruction Scheduling""
Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose, Oguz Ergin
ACM Transactions on Architecture and Code
Optimization (ACM TACO), Vol.3, No.2, June 2006, pp.156-181.
2005
- "Incremental Commit Groups for
Non-Atomic Trace Processing"
Matt T. Yourst, Kanad Ghose
38th IEEE/ACM Symposium on Microarchitecture
(MICRO-2005), Barcelona, November 2005, pp.67-80.
- "Instruction
Replication for Reducing Delays due to Inter-PE Communication Latency"
Aneesh Aggarwal, Manoj Franklin
IEEE Transactions on Computers, Volume 54, No 12,
December 2005, pp.1496-1507.
- "Reducing the
Power Dissipation of Register Alias Tables in High Performance
Processors"
Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose
IEE Proceedings, Computer and Digital Techniques, Volume
152, Issue 6, November 2005, pp.739-746.
- "Scalability of Instruction
Distribution Algorithms for On-Chip Clustering"
Aneesh Aggarwal, Manoj Franklin
IEEE Transactions on Parallel and Distributed Systems,
vol.16, No.10, October 2005, pp.944-955.
- "Improving
Adaptive Cache Leakage Reduction Techniques with Line Buffers"
Gurhan Kucuk, Kanad Ghose
2nd Watson Conference on Interaction between
Architecture, Circuits, and Compilers (P=ac2 Conference 2005), IBM
Research Center at Yorktown Heights, NY, September 2005.
- "Scalable, Low-Complexity
Instruction Schedulers for SMT Processors"
Joseph J. Sharkey, Deniz Balkan, Dmitry V. Ponomarev
2nd Watson Conference on Interaction between
Architecture, Circuits, and Compilers (P=ac2 Conference 2005), IBM
Research Center at Yorktown Heights, NY, September 2005.
- "Instruction Error Rate Modeling
for High Performance Microprocessors"
Aneesh Aggarwal
2nd Watson Conference on Interaction between
Architecture, Circuits, and Compilers (P=ac2 Conference 2005), IBM
Research Center at Yorktown Heights, NY, September 2005.
- "Optimal Resource Allocation for
Concurrent Error Detection Techniques in High Performance
Microprocessors"
Sumeet Kumar, Aneesh Aggarwal
2nd Watson Conference on Interaction between
Architecture, Circuits, and Compilers (P=ac2 Conference 2005), IBM
Research Center at Yorktown Heights, NY, September 2005.
- "An Adaptive
Technique for Reducing Leakage and Dynamic Power in Register Files and
Reorder Buffers"
Shadi T. Khasawneh, Kanad Ghose
PATMOS-2005, Belgium, September 2005.
- "Power-Efficient Wakeup Tag
Broadcast"
Joseph Sharkey, Kanad Ghose, Dmitry Ponomarev, Oguz Ergin
In 23rd IEEE International Conference on Computer Design
(ICCD'05) , San Jose, CA, October 2005.
- "Restrictive Compression Techniques
to Increase L1 Cache Capacity"
Prateek Pujara, Aneesh Aggarwal
In 23rd IEEE International Conference on Computer Design
(ICCD'05) , San Jose, CA, October 2005.
- "Non-Uniform
Instruction Scheduling"
Joseph Sharkey, Dmitry Ponomarev
In Euro-Par'05 Conference , Lisbon, Portugal, -
Published as LNCS 3648, August 2005, pp. 540-549. Acceptance rate - 31%
- "Instruction
Recirculation: Eliminating Counting Logic in Wakeup Free Schedulers"
Joseph Sharkey, Dmitry Ponomarev
In Euro-Par'05 Conference , Lisbon, Portugal, -
Published as LNCS 3648, August 2005, pp. 550-559. Acceptance rate - 31%
- "Instruction Packing: Reducing
Power and Delay of the Dynamic Scheduling Logic"
Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose, Oguz Ergin
In the IEEE/ACM International Symposium on Low Power
Electronics and Design (ISLPED'05), San Diego, CA, August 2005,
pp. 30-35. Acceptance rate for full papers - 9%
- "Reducing Latencies of Pipelined
Cache Accesses Through Set Prediction"
Aneesh Aggarwal
International Conference on Supercomputing (ICS'05) Boston,
MA, June 2005.
2004
- "Register Packing: Exploiting
Narrow-Width Operands for Reducing Register File Pressure"
Oguz Ergin, Deniz Balkan, Kanad Ghose, Dmitry Ponomarev
37th IEEE/ACM International Symposium on
Microarchitecture (MICRO-37), Portland, OR, December 2004.
- "Reducing Delay and Power
Consumption of the Wakeup Logic through Instruction Packing and Tag
Memoization"
Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose, Oguz Ergin
4th Workshop on Power-Aware Computer Systems (PACS'04),
held in conjunction with the 37th IEEE/ACM International Symposium on
Microarchitecture (MICRO-37), Portland, OR, December 2004.
Extended version appears in LNCS 3471.
- "Bit-Sliced Datapath for
Energy-Efficient High-Performance Microprocessors"
Sumeet Kumar, Prateek Pujara, Aneesh Aggarwal
4th Workshop on Power-Aware Computer Systems (PACS'04),
held in conjunction with the 37th IEEE/ACM International Symposium on
Microarchitecture (MICRO-37), Portland, OR, December 2004.
Extended version appears in LNCS 3471.
- "Increasing Processor Performance
Through Early Register Release"
Oguz Ergin, Deniz Balkan, Dmitry Ponomarev, Kanad Ghose
22nd IEEE International Conference on Computer Design
(ICCD'04), October 2004.
- "Defining Wakeup Width for
Efficient Dynamic Scheduling"
Aneesh Aggarwal, Manoj Franklin, Oguz Ergin
22nd IEEE International Conference on Computer Design
(ICCD'04), October 2004.
- "Selective Writeback: Improving Processor Performance and Energy-Efficiency"
Deniz Balkan, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose
1st IBM Watson Conference on Interaction between Architecture, Circuits,
and Compilers (P=ac2), Yorktown Heights, October 2004.
- "Predicting, Detecting and Exploiting Transient Values"
Deniz Balkan, Dmitry Ponomarev, Kanad Ghose
2nd Value Prediction Workshop, held in conjunction with ASLPOS 2004, Boston, MA, October
2004.
- "Energy-Efficient
Comparators for Superscalar Datapaths"
Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose
IEEE Transactions on Computers, vol.53, No. 7, July 2004,
pp.892-904.
- "Isolating
Short-Lived Operands for Energy Reduction"
Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose
IEEE Transactions on Computers, vol. 53, No. 6, June
2004, pp. 697-709.
- "Complexity-Effective Reorder
Buffer Designs for Superscalar Processors"
Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, Kanad Ghose
IEEE Transactions on Computers, vol.53, No. 6, June 2004,
pp.653-665.
- "Single FU Bypass Networks for
High Clock Rate Superscalar Processors"
Aneesh Aggarwal
In the International Conference on High Performance
Computing (HiPC'04), December 2004.
2003
- "Energy-Efficient Issue
Queue Design"
Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose, Peter Kogge
IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, vol. 11, No. 5, October 2003, pp. 789-800.
- "Distributed Reorder Buffer Schemes
for Low Power"
Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose
21st International Conference on Computer Design (ICCD'03),
San Jose, October 2003, pp.364-370.
- "Reducing Datapath Energy
Through the Isolation of Short-Lived Operands"
Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose
12th International Conference on Parallel Architectures
and Compilation Techniques (PACT'03), New Orleans, September 2003,
pp.258-268.
- "Reducing Reorder Buffer
Complexity Through Selective Operand Caching"
Gurhan Kucuk, Dmitry Ponomarev, Oguz Ergin, Kanad Ghose
International Symposium on Low-Power Electronics and
Design (ISLPED'03), Seoul, South Korea, August 2003, pp. 235-240.
- "Power Efficient Comparators
for Long Arguments in Superscalar Processors"
Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad Ghose
International Symposium on Low-Power Electronics and
Design (ISLPED'03), Seoul, South Korea, August 2003, pp. 378-383.
- "Energy Efficient Register
Renaming"
Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose
13th International Workshop on Power and Timing Modeling,
Optimization and Simulation (PATMOS'03), Torino, Italy, September
2003, Published as Lecture Notes in Computer Science, LNCS 2799,
pp.219-228
2002
- "A Circuit-Level Implementation of
Fast, Energy-Efficient CMOS Comparators for High-Performance
Microprocessors"
Oguz Ergin, Kanad Ghose, Gurhan Kucuk, Dmitry Ponomarev
20th IEEE International Conference on Computer Design
(ICCD'02), Freiburg, Germany, September 2002, pp.118-121.
- "Energy-Efficient Design of
the Reorder Buffer"
Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose
12th International Workshop on Power and Timing Modeling,
Optimization and Simulation (PATMOS'02), Seville, Spain,
September 2002. Published as Lecture Notes in Computer Science, LNCS
2451, pp.289-299.
- "Low-Complexity Reorder Buffer
Architecture"
Gurhan Kucuk, Dmitry Ponomarev, Kanad Ghose
16th ACM International Conference on Supercomputing
(ICS'02), New York, June 2002, pp. 57-66.
- "AccuPower: An Accurate Power
Estimation Tool for Superscalar Microprocessors"
Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose
5th Design, Automation and Test in Europe Conference
(DATE'02), Paris, France, March 2002, pp.124-129.
2001
- "Reducing Power Requirements of
Instruction Scheduling Through Dynamic Allocation of Multiple Datapath
Resources"
Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose
34th IEEE/ACM International Symposium on
Microarchitecture (MICRO-34), Austin, TX, December 2001, pp.
90-101.
- "Energy-Efficient Instruction
Dispatch Buffer Design for Superscalar Processors"
Gurhan Kucuk, Kanad Ghose, Dmitry V. Ponomarev and Peter M. Kogge
IEEE/ACM International Symposium on Low Power Electronics
and Design (ISLPED'01), Huntington Beach, CA, August 2001, pp.
237-242.
- "Dynamic Allocation of Datapath
Resources for Low Power"
Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose
Workshop on Complexity-Effective Design (WCED'01), 28th
International Symposium on Computer Architecture (ISCA-28),
Goteborg, Sweden, June 2001.
- "Power Reduction in Superscalar
Datapaths Through Dynamic Bit-Slice Activation"
Dmitry Ponomarev, Gurhan Kucuk, Kanad Ghose
International Workshop "Innovative Architecture for
Future Generation High-Performance Processors and Systems" (IWIA'01),
2001, pp.16-24
2000
- "Exploiting Bit-Slice
Inactivities for Reducing Energy Requirements of Superscalar Processors"
Kanad Ghose, Dmitry Ponomarev, Gurhan Kucuk, Andrew Flinders, Peter
Kogge, Nikzad Toomarian
Kool Chips Workshop, 33rd International Symposium on
Microarchitecture (MICRO-33), Monterey, CA, December 2000.
- "Reducing Energy Requirements for
Instruction Issue and Dispatch in Superscalar Microprocessors"
Kanad Ghose
International Symposium on Low Power Electronics and
Design (ISLPED'00), July 2000, pp.231-234.
1999
1997
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