Computer Architecture and
Power Aware Systems Research Group


PTLsim is a cycle accurate x86 microprocessor simulator and virtual machine for the x86 and x86-64 instruction sets. PTLsim models a modern superscalar out of order x86-64 compatible processor core at a configurable level of detail ranging from full-speed native execution on the host CPU all the way down to RTL level models of all key pipeline structures. In addition, the complete cache hierarchy, memory subsystem and supporting hardware devices are modeled with true cycle accuracy. PTLsim supports the full x86-64 instruction set of the Pentium 4+, Athlon 64 and similar machines with all extensions (x86-64, SSE/SSE2/SSE3, MMX, x87). It is currently the only tool available to the public to support true cycle accurate modeling of real x86 microarchitectures.

PTLsim is very different from most cycle accurate simulators used in research applications. It runs directly on the same platform it is simulating (an x86-64 or x86 machine running Linux) and is able to switch in and out of full out of order simulation mode and native x86-64 mode at any time completely transparent to the running user code. This lets users quickly profile a small section of the user code without the overhead of emulating the uninteresting parts. PTLsim runs unmodified 32-bit x86 and 64-bit x86-64 applications without special compilers or toolchains.

PTLsim comes in two flavors. The standard version runs any 32-bit or 64-bit single threaded userspace Linux application. PTLsim/X integrates with the Xen hypervisor to provide full system x86-64 simulation, multi-processor and multi-threading support, cycle accurate device and timing models, and much more.

Compared to competing simulators, PTLsim provides extremely high performance even when running in full cycle accurate out of order simulation mode. Even with its optimized core, PTLsim still allows a significant amount of flexibility for easy experimentation.

PTLsim is used extensively in our Computer Architecture and Power-Aware Systems (CAPS) research group at the State University of New York at Binghamton, in addition to hundreds of major universities, industry research labs and several well known microprocessor vendors including Intel and IBM.

M-Sim is a multi-threaded microarchitectural simulation environment with a detailed cycle-accurate model for the key pipeline structures. M-Sim is based on SimpleScalar 3.0d. At this point, only the Alpha AXP binaries are supported. M-Sim works on all computing platforms which support the original SimpleScalar.

M-Sim extends the SimpleScalar 3.0d in the following ways:

  • M-Sim includes cycle-accurate models for separate pipeline structures, such as the re-order buffer (ROB), issue queue, and separate integer and floating-point physical register files.
  • M-Sim explicitly models register renaming and the associated rename tables.
  • M-Sim supports single threaded execution (supserscalar mode) as well as the multithreded mode in which multiple threads of control are executed simultaneously, according to the Simultaneous Multithreaded (SMT) model. In the SMT mode, some processor structures (i.e. issue queue, physical register files, execution units, caches) are shared among the threads, and others (rename tables, ROBs, load/store queues) are private to each thread.
  • The latest version includes speculative instruction scheduling based on load-latency prediction, including the squash recover model used by the Alpha 21264 processor.



Copyright © 2005 CAPS, Designed by: Deniz Balkan & Joe Sharkey